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| IPD05N03LA G IPS05N03LA G IPF05N03LA G IPU05N03LA G OptiMOS(R)2 Power-Transistor Features * Ideal for high-frequency dc/dc converters * Qualified according to JEDEC1) for target application * N-channel, logic level * Excellent gate charge x R DS(on) product (FOM) * Superior thermal resistance * 175 C operating temperature * Pb-free lead plating; RoHS compliant Product Summary V DS R DS(on),max (SMD version) ID 25 5.1 50 V m A Type Type IPD05N03LA IPF05N03LA IPS05N03LA Package IPU05N03LA Marking IPD05N03LA Package P-TO252-3-11 P-TO252-3-23 P-TO252-3-11 P-TO251-3-11 05N03LA P-TO251-3-21 IPF05N03LA Ordering Code Q67042-S4144 Q67042-S P-TO252-3-23 Q67042-S 05N03LA Q67042-S4230 IPS05N03LA Marking 05N03LA 05N03LA 05N03LA P-TO251-3-11 05N03LA 05N03LA IPU05N03LA P-TO251-3-1 05N03LA Maximum ratings, at T j=25 C, unless otherwise specified Parameter Continuous drain current Symbol Conditions ID T C=25 C2) T C=100 C Pulsed drain current Avalanche energy, single pulse Reverse diode dv /dt Gate source voltage4) Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 I D,pulse E AS dv /dt V GS P tot T j, T stg T C=25 C T C=25 C3) I D=45 A, R GS=25 I D=50 A, V DS=20 V, di /dt =200 A/s, T j,max=175 C Value 50 50 350 300 6 20 94 -55 ... 175 55/175/56 mJ kV/s V W C Unit A Rev. 2.0 page 1 2006-05-11 IPD05N03LA G IPS05N03LA G Parameter Symbol Conditions min. Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA minimal footprint 6 cm2 cooling area5) Electrical characteristics, at T j=25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D=1 mA V GS(th) I DSS V DS=V GS, I D=50 A V DS=25 V, V GS=0 V, T j=25 C V DS=25 V, V GS=0 V, T j=125 C Gate-source leakage current Drain-source on-state resistance I GSS R DS(on) V GS=20 V, V DS=0 V V GS=4.5 V, I D=30 A V GS=4.5 V, I D=30 A, SMD version V GS=10 V, I D=30 A V GS=10 V, I D=30 A, SMD version Gate resistance Transconductance RG g fs |V DS|>2|I D|R DS(on)max, I D=30 A 25 1.2 1.6 0.1 Values typ. IPF05N03LA G IPU05N03LA G Unit max. 1.6 75 50 K/W 2 1 V A 31 10 10 6.9 6.7 4.4 4.2 1 62 100 100 8.6 8.4 5.3 5.1 S nA m 1) J-STD20 and JESD22 Current is limited by bondwire; with an R thJC=1.6 K/W the chip is able to carry 106 A. See figure 3 T j,max=150 C and duty cycle D <0.25 for V GS<-5 V 2) 3) 4) 5) 2 Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 m thick) copper area for drain connection. PCB is vertical in still air. Rev. 2.0 page 2 2006-05-11 IPD05N03LA G IPS05N03LA G Parameter Symbol Conditions min. Dynamic characteristics Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics 6) Gate to source charge Gate charge at threshold Gate to drain charge Switching charge Gate charge total Gate plateau voltage Gate charge total, sync. FET Output charge Reverse Diode Diode continous forward current Diode pulse current Diode forward voltage IS I S,pulse V SD T C=25 C V GS=0 V, I F=50 A, T j=25 C V R=15 V, I F=I S, di F/dt =400 A/s 0.91 Q gs Q g(th) Q gd Q sw Qg V plateau Q g(sync) Q oss V DS=0.1 V, V GS=0 to 5 V V DD=15 V, V GS=0 V V DD=15 V, I D=25 A, V GS=0 to 5 V 7.6 3.9 5.2 9.0 19 3.2 17 20 C iss C oss Crss t d(on) tr t d(off) tf V DD=15 V, V GS=10 V, I D=25 A, R G=2.7 V GS=0 V, V DS=15 V, f =1 MHz 2413 921 112 10 7.8 31 4.8 Values typ. IPF05N03LA G IPU05N03LA G Unit max. 3110 1225 167 15 12 38 6.0 pF ns 10 5.0 7.8 13 25 22 27 nC V nC 50 350 1.2 A V Reverse recovery charge Q rr - - 10 nC 6) See figure 16 for gate charge parameter definition Rev. 2.0 page 3 2006-05-11 IPD05N03LA G IPS05N03LA G 1 Power dissipation P tot=f(T C) 2 Drain current I D=f(T C); V GS10 V IPF05N03LA G IPU05N03LA G 100 90 80 70 60 60 50 40 P tot [W] 50 40 30 20 10 0 0 50 100 150 200 I D [A] 30 20 10 0 0 50 100 150 200 T C [C] T C [C] 3 Safe operating area I D=f(V DS); T C=25 C; D =0 parameter: t p 1000 1 s limited by on-state resistance 10 s 4 Max. transient thermal impedance Z thJC=f(t p) parameter: D =t p/T 10 100 1 0.5 Z thJC [K/W] 100 s I D [A] DC 1 ms 0.2 0.1 0.05 10 10 ms 0.1 0.02 0.01 single pulse 1 0.1 1 10 100 0.01 0 0 0 0 0 0 1 10-6 10-5 10-4 10-3 10-2 10-1 100 V DS [V] t p [s] Rev. 2.0 page 4 2006-05-11 IPD05N03LA G IPS05N03LA G 5 Typ. output characteristics I D=f(V DS); T j=25 C parameter: V GS 100 10 V IPF05N03LA G IPU05N03LA G 6 Typ. drain-source on resistance R DS(on)=f(I D); T j=25 C parameter: V GS 20 90 80 70 60 4.5 V 4.1 V 18 16 3.8 V 3V 3.2 V 3.5 V 3.8 V 4.1 V 14 R DS(on) [m] 12 10 8 6 I D [A] 50 3.5 V 40 30 3.2 V 4.5 V 20 3V 4 2 0 0 1 2 3 0 20 40 60 80 10 V 10 0 2.8 V 100 V DS [V] I D [A] 7 Typ. transfer characteristics I D=f(V GS); |V DS|>2|I D|R DS(on)max parameter: T j 100 8 Typ. forward transconductance g fs=f(I D); T j=25 C 80 70 80 60 60 50 g fs [S] 40 20 175 C 25 C I D [A] 40 30 20 10 0 0 1 2 3 4 5 0 0 10 20 30 40 50 60 V GS [V] I D [A] Rev. 2.0 page 5 2006-05-11 IPD05N03LA G IPS05N03LA G 9 Drain-source on-state resistance R DS(on)=f(T j); I D=30 A; V GS=10 V 10 Typ. gate threshold voltage V GS(th)=f(T j); V GS=V DS parameter: I D 10 9 8 7 2 2.5 IPF05N03LA G IPU05N03LA G 500 A 98 % R DS(on) [m] 6 5 4 3 2 1 0 -60 -20 20 V GS(th) [V] 1.5 50 A typ 1 0.5 0 60 100 140 180 -60 -20 20 60 100 140 180 T j [C] T j [C] 11 Typ. capacitances C =f(V DS); V GS=0 V; f =1 MHz 12 Forward characteristics of reverse diode I F=f(V SD) parameter: T j 10000 1000 Ciss Coss 1000 100 25 C 175 C 175 C, 98% C [pF] Crss I F [A] 25 C, 87% 100 10 10 0 5 10 15 20 25 30 1 0.0 0.5 1.0 1.5 2.0 V DS [V] V SD [V] Rev. 2.0 page 6 2006-05-11 IPD05N03LA G IPS05N03LA G 13 Avalanche characteristics I AS=f(t AV); R GS=25 parameter: Tj(start) 100 IPF05N03LA G IPU05N03LA G 14 Typ. gate charge V GS=f(Q gate); I D=25 A pulsed parameter: V DD 12 15 V 10 150 C 100 C 25 C 5V 20 V 8 10 V GS [V] 1 10 100 1000 I AV [A] 6 4 2 1 0 0 20 40 t AV [s] Q gate [nC] 15 Drain-source breakdown voltage V BR(DSS)=f(T j); I D=1 mA 16 Gate charge waveforms 29 V GS 28 27 26 Qg V BR(DSS) [V] 25 24 23 22 21 20 -60 -20 20 60 100 140 180 V g s(th) Q g(th) Q gs Q sw Q gd Q g ate T j [C] Rev. 2.0 page 7 2006-05-11 IPD05N03LA G IPS05N03LA G Package Outline PG-TO252-3-11: Outline PG-TO252-3-11 IPF05N03LA G IPU05N03LA G Footprint: Packaging: Rev. 2.0 page 8 2006-05-11 IPD05N03LA G IPS05N03LA G Package Outline PG-TO252-3-23: Outline PG-TO252-3-23 IPF05N03LA G IPU05N03LA G Footprint: Rev. 2.0 page 9 2006-05-11 IPD05N03LA G IPS05N03LA G Package Outline PG-TO251-3-11: Outline PG-TO251-3-11 IPF05N03LA G IPU05N03LA G PG-TO251-3-21: Outline Rev. 2.0 page 10 2006-05-11 IPD05N03LA G IPS05N03LA G Package Outline PG-TO251-3-11: Outline PG-TO251-3-21 IPF05N03LA G IPU05N03LA G PG-TO251-3-21: Outline Rev. 2.0 page 11 2006-05-11 IPD05N03LA G IPS05N03LA G IPF05N03LA G IPU05N03LA G Published by Infineon Technologies AG 81726 Munchen, Germany (c) Infineon Technologies AG 2006. All Rights Reserved. Attention please! The information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com ). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 2.0 page 12 2006-05-11 |
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